The present invention relates to a dynamic type memory device.
Generally, a dynamic type memory device in which bit lines are precharged to 1/2 of a power source voltage VC in a precharge cycle is known. For example, as understood from part of this kind of memory device shown in FIG. 1, this memory device is constituted such that one end of each of paired bit lines BL and BL is connected to a sense amplifier 12, capacitor CS is connected to bit line BL through MOS transistor Q1 whose gate is connected to word line WL, and capacitor CD is connected to bit line BL through MOS transistor Q.sub.5 whose gate is connected to dummy word line DWL. The other terminals of capacitors CS and CD are connected to fixed voltage terminal VA. The other ends of bit lines BL and BL are connected to each other by MOS transistor Q.sub.2 and are respectively connected through MOS transistors Q.sub.3 and Q.sub.4 to a predetermined voltage line VCL which is kept at, for example, 1/2 VC. An equalizing signal .phi..sub.EQ is supplied to gates of MOS transistors Q.sub.2 to Q.sub. 4. Capacitors CS and CD are formed to have the same capacitance. MOS transistor Q.sub.1 and capacitor CS constitute a memory cell 11. MOS transistor Q.sub.5 and capacitor CD constitute a dummy cell 13.
The operation of the memory device shown in FIG. 1 will be described with reference to signal waveforms shown in FIGS. 2(A) to 2(E).
In this memory device, when equalizing signal .phi..sub.EQ is at a high level, MOS transistors Q.sub.2 to Q.sub.4 are made conductive and both bit lines BL and BL are precharged to the level of 1/2 VC. After data is written into memory cell 11, the voltage of 1/2 VC is written into dummy cell 13. After a row address strobe signal RAS is set to a low level at time t1 as shown in FIG. 2(A), when equalizing signal .phi..sub.EQ becomes low at time t.sub.2 as shown in FIG. 2(C), MOS transistors Q.sub.2 to Q.sub.4 are made non-conductive, so that bit lines BL and BL are isolated from each other. When the potentials of dummy word line DWL and word line WL are set to a high level as shown in FIGS. 2(D) and 2(B), the data in dummy cell 13 and memory cell 11 are read out and outputted onto bit lines BL and BL respectively, so that the potentials of bit lines BL and BL will change as shown in FIG. 2(E). The difference between the potentials of bit lines BL and BL is amplified by sense amplifier 12 and corresponding readout data is taken out from sense amplifier 12. Next, row address strobe signal RAS is set to a high level and the potential of word line WL is set to a low level and thereafter equalizing signal .phi..sub.EQ is set to a high level. Thus, MOS transistors Q.sub.2 to Q.sub.4 are made conductive and both potentials of bit lines BL and BL are set to 1/2 VC. After the vo1tage of the 1/2 VC level is written into dummy cell 13, the potential of dummy word line DWL is set low as shown in FIG. 2(D).
In the memory device shown in FIG. 1, to certainly write the voltage of 1/2 VC into dummy cell 13, it is necessary to set dummy word line DWL to a high potential. A voltage step-up circuit needs to be connected to dummy word line DWL for this purpose, causing the structure of this memory device to be complicated. In addition, to write the voltage of 1/2 VC into dummy cell 13, it is necessary to hold dummy word line DWL at a high level for a predetermined time as well even after row address strobe signal RAS is set to a high level. Therefore, a special control circuit is needed to control the potential of dummy word line DWL.
A memory device shown in FIG. 3 is constituted similarly to that shown in FIG. 1 except that dummy cell 13 and MOS transistors Q.sub.3 and Q.sub.4 are removed. This memory device operates in accordance with signal waveforms shown in FIGS. 4A to 4D. Namely, in this memory device, after row address strobe signal RAS is set at a low level as shown in FIG. 4(A), equalizing signal .phi..sub.EQ is set at a high level as shown in FIG. 4(C). Thereafter, when the potential of word line WL is set at a high level as shown in FIG. 4(B), the data in memory cell 11 is read out and outputted onto bit lines BL and BL and the potentials of bit lines BL and BL are changed in accordance with the data read out as shown in FIG. 4(D). By equalizing the potentials of bit lines BL and BL in initial time of each readout operation as described above, data can be read out without being influenced due to the fluctuation of the power source voltage. However, data readout operation cannot be started until the potentials of bit lines BL and BL are equalized after strobe signal RAS is set at a low level, so that the access time eventually becomes long.